The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 16, 2013
Filed:
Jul. 01, 2010
Tadashi Kawashima, Tokyo, JP;
Masahiro Yoshikawa, Tokyo, JP;
Akira Inoue, Tokyo, JP;
Yoshiya Yoshida, Tokyo, JP;
Kazuhiro Iriguchi, Tokyo, JP;
Toshiyuki Isami, Tokyo, JP;
Tadashi Kawashima, Tokyo, JP;
Masahiro Yoshikawa, Tokyo, JP;
Akira Inoue, Tokyo, JP;
Yoshiya Yoshida, Tokyo, JP;
Kazuhiro Iriguchi, Tokyo, JP;
Toshiyuki Isami, Tokyo, JP;
Sumco Corporation, Tokyo, JP;
Abstract
It is an object to provide an epitaxial silicon wafer that is provided with an excellent gettering ability in which a polysilicon layer is formed on the rear face side of a silicon crystal substrate into which phosphorus (P) and germanium (Ge) have been doped. A PBS forming step for growing a polysilicon layer is executed on the rear face side of a silicon crystal substrate into which phosphorus and germanium have been doped at a high concentration to execute a baking treatment. After a surface layer of the silicon crystal substrate is then polished up to a predetermined amount, a silicon epitaxial layer is grown by a CVD method. By the above steps, the number of LPDs (caused by an SF) that occur on the surface of the epitaxial silicon wafer due to the SF can be greatly reduced.