The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 09, 2013
Filed:
Jun. 17, 2011
Charles J. Alpert, Austin, TX (US);
Zhuo LI, Cedar Park, TX (US);
Gi-joon Nam, Austin, TX (US);
David A. Papa, Austin, TX (US);
Chin Ngai Sze, Austin, TX (US);
Natarajan Viswanathan, Austin, TX (US);
Brian C. Wilson, Rochester, MN (US);
Charles J. Alpert, Austin, TX (US);
Zhuo Li, Cedar Park, TX (US);
Gi-Joon Nam, Austin, TX (US);
David A. Papa, Austin, TX (US);
Chin Ngai Sze, Austin, TX (US);
Natarajan Viswanathan, Austin, TX (US);
Brian C. Wilson, Rochester, MN (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
The input slew at a selected gate of an integrated circuit design is computed by assigning a default slew rate to the output gate of a previous logic stage which is greater than a median slew rate for the design. This default slew rate is propagated through the logic stage to generate an input slew rate at the selected gate. The default slew rate corresponds to a predetermined percentile applied to a limited sample of preliminary slew rates for randomly selected gates in the design. The default slew rate is adjusted as a function of known characteristics of the wirelength from the output gate to a first gate in the second logic stage. The delay of the selected gate is calculated based on the input slew rate. The input slew rate can be stored during one optimization iteration and used as a default slew rate during a later optimization iteration.