The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 09, 2013
Filed:
Dec. 29, 2010
Eric S. Carman, Cernex, FR;
Philippe Bruno Bauser, Divonne-les-Bains, FR;
Jean-michel Daga, Peynier, FR;
Eric S. Carman, Cernex, FR;
Philippe Bruno Bauser, Divonne-les-Bains, FR;
Jean-Michel Daga, Peynier, FR;
Micron Technology, Inc., Boise, ID (US);
Abstract
Techniques for controlling a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for controlling a semiconductor memory device including applying a plurality of voltage potentials to a plurality of memory cells arranged in an array of rows and columns. Applying the plurality of voltage potentials to the plurality of memory cells may include applying a first voltage potential to a first memory cell in a row of the array via a first respective bit line and a first switch transistor, applying a second voltage potential to a second memory cell in the row of the array via a second respective bit line and a second switch transistor, and applying a third voltage potential to at least one third memory cell in the row of the array via at least one third respective bit line and at least one third switch transistor, wherein the at least one third memory cell may be located between the first memory cell and the second memory cell in the row of the array.