The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 09, 2013
Filed:
Jul. 10, 2008
Heimo Scheucher, Langegg, AT;
Guido Albermann, Hamburg, DE;
David Ceccarelli, Graz, AT;
NXP B.V., Eindhoven, NL;
Abstract
Integrated circuits () on a wafer comprise a wafer substrate () and a structure applied on a surface () of the wafer substrate (). The structure forms a plurality of integrated circuits () formed on the wafer substrate () and the integrated circuits () are separated by saw lines (). The structure comprises a plurality of superposed layers (-) formed on the wafer substrate () and a top layer () formed on the superposed layers (-). The integrated circuit () on the wafer further comprise a plurality of alignment marks () intended for aligning a separating device () for separating the integrated circuits () on the wafer into individual integrated circuits () during a separation process, wherein the alignment marks () are formed from at least one of the superposed layers (-).