The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 02, 2013
Filed:
Dec. 07, 2010
Atul V. Ghia, San Jose, CA (US);
Christopher P. Wyland, Livermore, CA (US);
Ketan Sodha, Fremont, CA (US);
Paul T. Sasaki, Sunnyvale, CA (US);
Jian Tan, Fremont, CA (US);
Paul Y. Wu, Saratoga, CA (US);
Romi Mayder, San Jose, CA (US);
Atul V. Ghia, San Jose, CA (US);
Christopher P. Wyland, Livermore, CA (US);
Ketan Sodha, Fremont, CA (US);
Paul T. Sasaki, Sunnyvale, CA (US);
Jian Tan, Fremont, CA (US);
Paul Y. Wu, Saratoga, CA (US);
Romi Mayder, San Jose, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
In one embodiment, an integrated circuit (IC) is presented. The IC includes first and second sets of power distribution lines formed in the IC. The IC includes first and second capacitors formed in one or more layers of the IC. A first plurality of vias couple a first input of the first and second capacitors to the first set of power distribution lines, and a second plurality of vias couple a second input of the first and second capacitors to the second set of power distribution lines. The first capacitor and the first plurality of vias and the second plurality of vias coupled thereto having an equivalent series resistance greater than an equivalent series resistance of the second capacitor and the first plurality of vias and the second plurality of vias coupled thereto.