The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 02, 2013
Filed:
May. 04, 2011
Method for integrating sonos non-volatile memory into a sub-90 nm standard cmos foundry process flow
Patrick Bruckner Shea, Washington, DC (US);
Dennis Adams, Gambrills, MD (US);
Michael Rennie, Mechanicsville, VA (US);
Joseph Terence Smith, Columbia, MD (US);
Patrick Bruckner Shea, Washington, DC (US);
Dennis Adams, Gambrills, MD (US);
Michael Rennie, Mechanicsville, VA (US);
Joseph Terence Smith, Columbia, MD (US);
Northrop Grumman Systems Corporation, Falls Church, VA (US);
Abstract
An embodiment of a method is disclosed to integrate silicon oxide nitride oxide silicon (SONOS) non-volatile memory (NVM) into a standard sub-90 nm complementary metal oxide semiconductor (CMOS) semiconductor foundry process flow. An embodiment of the method adds a few additional steps to a standard CMOS foundry process flow and makes minor changes to the rest of the baseline CMOS foundry process flow to form a new process module that includes both CMOS devices and an embedded SONOS NVM. An embodiment of the method utilizes new material sets (which are not utilized at larger nodes) that enhance NVM performance by improving charge tunneling behavior and reducing leakage currents. Furthermore, an embodiment of the method integrates CMOS with SONOS NVM at ever-shrinking dimensions while enhancing the NVM performance, without performing extra, costly processing steps.