The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 02, 2013
Filed:
Jan. 25, 2010
Jin-bum Kim, Seoul, KR;
Wook-je Kim, Gwacheon-si, KR;
Yu-gyun Shin, Hwaseong-si, KR;
Kwan-heum Lee, Suwon-si, KR;
Sun-ghil Lee, Yongin-si, KR;
Jin-bum Kim, Seoul, KR;
Wook-je Kim, Gwacheon-si, KR;
Yu-gyun Shin, Hwaseong-si, KR;
Kwan-heum Lee, Suwon-si, KR;
Sun-ghil Lee, Yongin-si, KR;
Abstract
Provided is a simplified method of manufacturing a semiconductor device having a stress creating layer. A first conductive first impurity region is formed on a semiconductor substrate on both sides of a first gate of a first area of the semiconductor substrate, and a second conductive second impurity region is formed on the semiconductor substrate on both sides of a second gate of a second area. First and second spacers are formed on sidewalls of the first and second gates, respectively. First and second semiconductor layers are formed in portions of the semiconductor substrate so as to contact the first and second impurity regions, respectively. The second semiconductor layer is removed. First and second barrier layers are formed in the first and second contact holes of the insulation layer, respectively.