The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 02, 2013

Filed:

Jan. 25, 2007
Applicants:

Yasuo Fukuhara, Osaka, JP;

Tomoaki Watanabe, Mino, JP;

Mao Yamaguchi, Koriyama, JP;

Yuki Kitai, Moriguchi, JP;

Hiroaki Fujiwara, Ikoma, JP;

Inventors:

Yasuo Fukuhara, Osaka, JP;

Tomoaki Watanabe, Mino, JP;

Mao Yamaguchi, Koriyama, JP;

Yuki Kitai, Moriguchi, JP;

Hiroaki Fujiwara, Ikoma, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
B32B 7/12 (2006.01);
U.S. Cl.
CPC ...
Abstract

The invention relates to a prepreg, obtained by impregnating a base material with an epoxy resin composition containing an epoxy resin (A), a curing agent (B), an accelerator (C), a phenoxy resin (D), and an inorganic filler (E) and semi-hardening the impregnated material, wherein the inorganic filler (E) has an average particle diameter of 3 μm or less. When a circuit with a narrow wire distance is formed on a surface of a insulator substrate composed of such a prepreg by using a method of forming the circuit by plating process, an amount of the plating remaining on the insulator substrate surface at the circuit contour periphery can be reduced. As a result, it leads to stabilization of inter-circuit insulation resistance and increase in a yield during production of printed wiring boards.


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