The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 26, 2013

Filed:

Oct. 26, 2008
Applicant:

Sabyasachi Das, Santa Clara, CA (US);

Inventor:

Sabyasachi Das, Santa Clara, CA (US);

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 7/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A full subtractor cell is disclosed including an XNOR gate having first and second inputs coupled to first and second bits; an XOR gate having first and second inputs coupled to an XNOR gate output and a carry input bit; a first AND gate having first and second inputs coupled to an XNOR gate output and the carry input bit; an inverter gate having an input coupled to the second bit to generate a complemented second bit; a second AND gate having first and second inputs coupled to the first bit and an inverter output to receive the complemented second bit; and an OR gate having first and second inputs coupled to a first AND gate output and a second AND gate output. An XOR gate output and an OR gate output generate the sum output bit and the carry output bit.


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