The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 26, 2013

Filed:

Nov. 12, 2010
Applicants:

Bong-soo Kim, Seongnam-si, KR;

Kwang-youl Chun, Seoul, KR;

Sang-bin Ahn, Incheon, KR;

Inventors:

Bong-Soo Kim, Seongnam-si, KR;

Kwang-Youl Chun, Seoul, KR;

Sang-Bin Ahn, Incheon, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Integrated circuit devices include a semiconductor substrate having a plurality of trench isolation regions therein that define respective semiconductor active regions therebetween. A trench is provided in the semiconductor substrate. The trench has first and second opposing sidewalls that define opposing interfaces with a first trench isolation region and a first active region, respectively. A first electrical interconnect is provided at a bottom of the trench. An electrically insulating capping pattern is provided, which extends between the first electrical interconnect and a top of the trench. An interconnect insulating layer is also provided, which lines the first and second sidewalls and bottom of the trench. The interconnect insulating layer extends between the first electrical interconnect and the first active region. A recess is provided in the first active region. The recess has a sidewall that defines an interface with the interconnect insulating layer. A second electrical interconnect is also provided, which extends on: (i) an upper surface of the first trench isolation region, (ii) the electrically insulating capping pattern; and (iii) the sidewall of the recess. The first and second electrical interconnects extend across the semiconductor substrate in first and second orthogonal directions, respectively.


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Kim, Bong-Soo. (2013). Semiconductor device and semiconductor module including the same (U.S. Patent No. 8405185). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8405185

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