The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8404531 B1

PDF
Full Text
Expired
Date of Patent:
Mar. 26, 2013

Filed:

Jan. 12, 2012
Applicants:

Yung-fa Lin, Hsinchu, TW;

Shou-yi Hsu, Hsinchu, TW;

Meng-wei Wu, Hsinchu, TW;

Yi-chun Shih, Hsinchu, TW;

Main-gwo Chen, Hsinchu, TW;

Inventors:

Yung-Fa Lin, Hsinchu, TW;

Shou-Yi Hsu, Hsinchu, TW;

Meng-Wei Wu, Hsinchu, TW;

Yi-Chun Shih, Hsinchu, TW;

Main-Gwo Chen, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/337 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for fabricating a power transistor includes: (a) forming a trench in a substrate with a first electrical type; (b) diffusing second electrical type carriers into the substrate from the trench such that the substrate is formed into a first part and a second part that is diffused with the second electrical type carriers and that adjoins the trench, the first and second parts being crystal lattice continuous to each other; (c) forming a filling portion in the trench, the filling portion adjoining the second part; (d) performing a carrier-implanting process in the second part and the filling portion; and (e) forming over the substrate a gate structure that has a dielectric layer and a conductive layer.


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