The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 19, 2013

Filed:

Dec. 31, 2010
Applicants:

Stephan Meier, Sunnyvale, CA (US);

Robert Hathaway, Sunnyvale, CA (US);

Evan Gewirtz, San Ramon, CA (US);

Brian Alleyne, Los Gatos, CA (US);

Edward Ho, Fremont, CA (US);

Inventors:

Stephan Meier, Sunnyvale, CA (US);

Robert Hathaway, Sunnyvale, CA (US);

Evan Gewirtz, San Ramon, CA (US);

Brian Alleyne, Los Gatos, CA (US);

Edward Ho, Fremont, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/10 (2006.01);
U.S. Cl.
CPC ...
Abstract

A network element that includes multiple memory types and memory sizes translates a logical memory address into a physical memory address. A memory access request is received for a data structure with a logical memory address that includes a region identifier that identifies a region that is mapped to one or more memories and is associated with a set of one or more region attributes whose values are based on processing requirements provided by a software programmer and the available memories of the network element. The network element accesses the region mapping table entry corresponding to the region identifier and, using the region attributes that are associated with the region, determines an access target for the request, determines a physical memory address offset within the access target, and generates a physical memory address. The access target includes a target class of memory, an instance within the class of memory, and a particular physical address space of the instance within the class of memory. The physical memory address includes a network routing information portion that includes information to route the physical memory address to the target instance, and includes an address payload portion that includes information to identify the physical address space identified by the subtarget and the physical memory address offset.


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