The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 19, 2013

Filed:

Nov. 29, 2010
Applicants:

Hoon Cho, Santa Clara, CA (US);

Kiran Pangal, Fremont, CA (US);

Krishna K. Parat, Palo Alto, CA (US);

Neal R. Mielke, Los Altos Hills, CA (US);

Pranav Kalavade, San Jose, CA (US);

Iwen Chao, Sacramento, CA (US);

Inventors:

Hoon Cho, Santa Clara, CA (US);

Kiran Pangal, Fremont, CA (US);

Krishna K. Parat, Palo Alto, CA (US);

Neal R. Mielke, Los Altos Hills, CA (US);

Pranav Kalavade, San Jose, CA (US);

Iwen Chao, Sacramento, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method and apparatus for improving the endurance of flash memories. In one embodiment of the invention, a high electric field is provided to the control gate of a flash memory module. The high electric field applied to the flash memory module removes trapped charges between a control gate and an active area of the flash memory module. In one embodiment of the invention, the high electric field is applied to the control gate of the flash memory module prior to an erase operation of the flash memory module. By applying a high electric field to the control gate of the flash memory module, embodiments of the invention improve the Program/Erase cycling degradation of the single-level or multi-level cells of the flash memory module.


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