The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 12, 2013

Filed:

Dec. 31, 2009
Applicants:

Nisha Talagala, Livermore, CA (US);

Berry Kercheval, Palo Alto, CA (US);

Martin Patterson, Menlo Park, CA (US);

Edward Pernicka, Palo Alto, CA (US);

James Bowen, Santa Clara, CA (US);

Inventors:

Nisha Talagala, Livermore, CA (US);

Berry Kercheval, Palo Alto, CA (US);

Martin Patterson, Menlo Park, CA (US);

Edward Pernicka, Palo Alto, CA (US);

James Bowen, Santa Clara, CA (US);

Assignee:

Violin Memory, Inc., Mountain View, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A multi-tiered cache manager and methods for managing multi-tiered cache are described. Multi-tiered cache manager causes cached data to be initially stored in the RAM elements and selects portions of the cached data stored in the RAM elements to be moved to the flash elements. Each flash element is organized as a plurality of write blocks having a block size and wherein a predefined maximum number of writes is permitted to each write block. The portions of the cached data may be selected based on a maximum write rate calculated from the maximum number of writes allowed for the flash device and a specified lifetime of the cache system.

Published as:
US2011145479A1; WO2011081957A2; WO2011081957A3; KR20120120186A; EP2519883A2; CN102812444A; US8397016B2; US2013262752A1; RU2012132643A; EP2519883A4; EP2519883B1; KR101726824B1;

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