The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 12, 2013

Filed:

Mar. 25, 2010
Applicants:

Po-feng Tsai, Taipei, TW;

Andy Tsen, Chung-Ho, TW;

JO Fei Wang, Hsin-Chu, TW;

Jong-i Mou, Hsinpu Township, Hsinchu County, TW;

Inventors:

Po-Feng Tsai, Taipei, TW;

Andy Tsen, Chung-Ho, TW;

Jo Fei Wang, Hsin-Chu, TW;

Jong-I Mou, Hsinpu Township, Hsinchu County, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 19/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present disclosure provides a method of fabricating a semiconductor device. The method includes collecting a plurality of manufacturing data sets from a plurality of semiconductor processes, respectively. The method includes normalizing each of the manufacturing data sets in a manner so that statistical differences among the manufacturing data sets are reduced. The method includes establishing a database that includes the normalized manufacturing data sets. The method includes normalizing the database in a manner so that the manufacturing data sets in the normalized database are statistically compatible with a selected one of the manufacturing data sets. The method includes predicting performance of a selected one of the semiconductor processes by using the normalized database. The selected semiconductor process corresponds to the selected manufacturing data set. The method includes controlling a semiconductor processing machine in response to the predicted performance.


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Tsai, Po-Feng. (2013). Method and system for implementing virtual metrology in semiconductor fabrication (U.S. Patent No. 8396583). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8396583

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