The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8395963 B1

PDF
Full Text
Expired
Date of Patent:
Mar. 12, 2013

Filed:

Dec. 09, 2010
Applicants:

Derick G. Behrends, Rochester, MN (US);

Todd A. Christensen, Rochester, MN (US);

Travis R. Hebig, Rochester, MN (US);

Daniel M. Nelson, Rochester, MN (US);

Inventors:

Derick G. Behrends, Rochester, MN (US);

Todd A. Christensen, Rochester, MN (US);

Travis R. Hebig, Rochester, MN (US);

Daniel M. Nelson, Rochester, MN (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 8/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A circuit and method erase at power-up all data stored in a DRAM chip for increased data security. All the DRAM memory cells are erased by turning on the transistors for the DRAM storage cells simultaneously by driving the wordlines of all the cells to an activated state. With all the devices turned on, the data stored in the memory cells is erased as the voltage of all the cells connected to a common bitline coalesce to a single value. In a preferred embodiment, the wordlines are all turned on simultaneously during a power on reset period. Preferably a power on reset signal is used to drive each logic gate of the pre-decoder portion of the address decoder in order to assert all the wordlines.


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