The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 12, 2013

Filed:

Oct. 07, 2010
Applicants:

Zvi Or-bach, San Jose, CA (US);

Brian Cronquist, San Jose, CA (US);

Israel Beinglass, Sunnyvale, CA (US);

Jan Lodewijk DE Jong, Cupertino, CA (US);

Deepak C. Sekar, San Jose, CA (US);

Zeev Wurman, Palo Alto, CA (US);

Inventors:

Zvi Or-Bach, San Jose, CA (US);

Brian Cronquist, San Jose, CA (US);

Israel Beinglass, Sunnyvale, CA (US);

Jan Lodewijk de Jong, Cupertino, CA (US);

Deepak C. Sekar, San Jose, CA (US);

Zeev Wurman, Palo Alto, CA (US);

Assignee:

MonolithIC 3D Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 21/8234 (2006.01); H01L 21/76 (2006.01); H01L 29/76 (2006.01); H01L 29/772 (2006.01); H01L 25/065 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor device including a first single crystal layer with first transistors and a first alignment mark; at least one metal layer overlying the first single crystal layer, wherein the at least one metal layer includes copper or aluminum; and a second layer including activated dopant regions, the second layer overlying the at least one metal layer, wherein the second layer includes second transistors, wherein the second transistors are processed aligned to the first alignment mark with less than 100 nm alignment error, and the second transistors include mono-crystal, horizontally-oriented transistors.


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