The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 12, 2013
Filed:
May. 10, 2010
Yih-chyun Kao, Hsin-Chu, TW;
Chun-nan Lin, Hsin-Chu, TW;
Li-kai Chen, Hsin-Chu, TW;
Wen-ching Tsai, Hsin-Chu, TW;
Yih-Chyun Kao, Hsin-Chu, TW;
Chun-Nan Lin, Hsin-Chu, TW;
Li-Kai Chen, Hsin-Chu, TW;
Wen-Ching Tsai, Hsin-Chu, TW;
Au Optronics Corp., Hsin-Chu, TW;
Abstract
A semiconductor device structure on a substrate and a manufacture method thereof is provided. The semiconductor device structure includes an oxide semiconductor transistor and a passivation layer containing free hydrogen. The semiconductor device structure is formed by following steps. A gate electrode is formed on the substrate. A gate dielectric layer covers the gate electrode. A source electrode is formed on the gate dielectric layer. A drain electrode is formed on the gate dielectric layer and separated from the source electrode and thereby forming a channel distance. An oxide semiconductor layer is formed on the gate dielectric layer, the source electrode and the drain electrode and between the source electrode and the drain electrode. The oxide semiconductor layer is further electrically connected with the source electrode and the drain electrode. A passivation layer covers the oxide semiconductor layer, the source electrode and the drain electrode. The passivation layer has a groove formed therein, and the groove surrounds the oxide semiconductor layer.