The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 05, 2013
Filed:
Dec. 22, 2006
Lance Hacking, Austin, TX (US);
Belliappa Kuttanna, Austin, TX (US);
Rajesh Patel, Austin, TX (US);
Ashish Choubal, Austin, TX (US);
Terry Fletcher, Rancho Cordova, CA (US);
Steven S. Varnum, Tigard, OR (US);
Binta Patel, Austin, TX (US);
Lance Hacking, Austin, TX (US);
Belliappa Kuttanna, Austin, TX (US);
Rajesh Patel, Austin, TX (US);
Ashish Choubal, Austin, TX (US);
Terry Fletcher, Rancho Cordova, CA (US);
Steven S. Varnum, Tigard, OR (US);
Binta Patel, Austin, TX (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A method to reduce idle leakage power in I/O pins of an integrated circuit using external circuitry. Initially, I/O pins on a package are subdivided into those that will also remain powered up and those that will power down during idle state. When a system enters a low power mode, a signal is sent to the external circuitry. The signal notifies the I/O pins that always remain powered up to notify the external circuitry to power down the other set of I/O pins.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile