The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 05, 2013

Filed:

Oct. 26, 2009
Applicants:

Tetsuaki Okahiro, Tokyo, JP;

Hiromasa Noda, Tokyo, JP;

Jun Suzuki, Tokyo, JP;

Inventors:

Tetsuaki Okahiro, Tokyo, JP;

Hiromasa Noda, Tokyo, JP;

Jun Suzuki, Tokyo, JP;

Assignee:

Elpida Memory, Inc., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/22 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor memory device comprises a plurality of memory cell mats, a plurality of sub-word driver regions and a plurality of sense amplifier regions, a plurality of intersection regions, a sub-amplifier, and a start signal (a control signal) supply circuit (a sub-amplifier control circuit). A plurality of sub-word driver regions and a plurality of sense amplifier regions are disposed adjacent to the plurality of memory cell mats. A plurality of intersection regions are intersection regions between the plurality of sub-word driver regions and the plurality of sense amplifier regions. The sub-amplifier is disposed in a first intersection region among the plurality of intersection regions. The start signal supply circuit is disposed in a second intersection region among the plurality of intersection regions, and supplies a start signal (a control signal) of the sub-amplifier to the sub-amplifier based on a sub-amplifier timing signal supplied from the extending direction of the sub-word driver region.


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