The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 05, 2013
Filed:
Dec. 21, 2009
Daniel Elmhurst, Folsom, CA (US);
Giovanni Santin, Rieti, IT;
Michele Incarnati, Gioia dei Marsi, IT;
Violante Moschiano, Bacoli, IT;
Ercole Diiorio, Scurcola Marsicana, IT;
Daniel Elmhurst, Folsom, CA (US);
Giovanni Santin, Rieti, IT;
Michele Incarnati, Gioia dei Marsi, IT;
Violante Moschiano, Bacoli, IT;
Ercole Diiorio, Scurcola Marsicana, IT;
Intel Corporation, Santa Clara, CA (US);
Abstract
In a method of operation, a flash memory cell coupled to a bit-line is programmed, a word-line voltage is coupled to the flash memory cell, a first voltage pulse is coupled to a bias transistor coupled between the bit-line and a sense capacitance at a first time to couple the bit-line to the sense capacitance to generate data to indicate the state of the flash memory cell, a second voltage pulse is coupled to the bias transistor at a second time having a second magnitude that is different from a first magnitude of the first voltage pulse, and a third voltage pulse is coupled to the bias transistor at a third time having a third magnitude that is different from the second magnitude of the second voltage pulse. In a method of operation, the second voltage pulse occurs a first delay period after the first voltage pulse and the third voltage pulse occurs a second delay period after the second voltage pulse, the second delay period being different from the first delay period.