Two-shelf interconnect

Abstract

Consistent with the present disclosure, a package is provided that includes a housing having a recessed portion to accommodate an integrated circuit or chip. The housing has an inner periphery that defines or delineates the recessed portion. The inner periphery may be stepped and includes first and second surfaces that are spaced vertically from one another and extend in respective parallel planes, for example, to thereby constitute first and second shelves. First bonding pads or contacts ('housing pads') may be provided on the first surface, which may electrically connect or interconnect with first pads on the integrated circuit ('IC pads'), and second housing pads may be provided on the second surface, which can electrically connect or interconnect with second IC pads. Thus, the IC pads connect to corresponding housing pads on the inner periphery of the housing that are above and below one another. Since the housing pads are not provided on the same surface, the number of housing pads on each step or shelf of the periphery can be reduced, and the housing pads can be spaced from one another by a spacing or pitch that is greater than that of the IC pads. Accordingly, the dimensions and spacing of the housing pads may comply with relevant design rules, while providing connection to an increased number of IC pads.