The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 26, 2013
Filed:
Apr. 14, 2011
Parijat Biswas, Bangalore, IN;
Raghurama Krishna Srigiriraju, Bangalore, IN;
Alexandru Seibulescu, San Mateo, CA (US);
Jayant Nagda, Fremont, CA (US);
Parijat Biswas, Bangalore, IN;
Raghurama Krishna Srigiriraju, Bangalore, IN;
Alexandru Seibulescu, San Mateo, CA (US);
Jayant Nagda, Fremont, CA (US);
Synopsys, Inc., Mountain View, CA (US);
Abstract
In a method for increasing coverage convergence during verification of a design for an integrated circuit, multiple simulation runs can be performed. Symbolic variables and symbolic expressions can be generated for the variables and the variable expressions in the hardware code of the design and a test bench. Exemplary hardware code can include the hardware description language (HDL) code and/or the hardware verification language (HVL) code. Symbolic properties, which are derived from propagating the symbolic variables and symbolic expressions through the design and the test bench during the multiple simulation runs, can be collected. Coverage information from the multiple simulation runs can be analyzed to identify coverage points to be targeted. At this point, for each identified coverage point, the constraints resulting from the collected symbolic properties can be solved to generate directed stimuli for the design. These directed stimuli can increase the coverage convergence.