The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 26, 2013
Filed:
Jun. 16, 2010
Sai Lalith Chaitanya Ambatipudi, San Jose, CA (US);
Seu Wah Low, San Jose, CA (US);
Christopher J. Borrelli, Campbell, CA (US);
Loren Jones, Aromas, CA (US);
Sai Lalith Chaitanya Ambatipudi, San Jose, CA (US);
Seu Wah Low, San Jose, CA (US);
Christopher J. Borrelli, Campbell, CA (US);
Loren Jones, Aromas, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
Circuits and methods are provided for estimating a latency through a FIFO buffer. A first detector detects first instances of a pattern in first data values serially written to a write port of the FIFO buffer. A second detector detects second instances of the pattern in second data values serially read from a read port of the FIFO buffer. The second data values are the first data values delayed by the latency through the FIFO buffer. A counter counts a count of active transitions of a sample clock signal. The counter starts on each detected first instance and stops on each detected second instances. The count provides an estimate of the latency of the FIFO buffer.