The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 26, 2013
Filed:
Aug. 14, 2009
John C. Arnold, Ridgefield, CT (US);
Glenn A. Biery, Staatsburg, NY (US);
Alessandro C. Callegari, Yorktown Heights, NY (US);
Tze-chiang Chen, Yorktown Heights, NY (US);
Michael P. Chudzik, Danbury, CT (US);
Bruce B. Doris, Brewster, NY (US);
Michael A. Gribelyuk, Stamford, CT (US);
Young-hee Kim, Yorktown Heights, NY (US);
Barry P. Linder, Hastings-on-Hudson, NY (US);
Vijay Narayanan, New York, NY (US);
Joseph S. Newbury, Irvington, NY (US);
Vamsi K. Paruchuri, New York, NY (US);
Michelle L. Steen, Danbury, CT (US);
John C. Arnold, Ridgefield, CT (US);
Glenn A. Biery, Staatsburg, NY (US);
Alessandro C. Callegari, Yorktown Heights, NY (US);
Tze-Chiang Chen, Yorktown Heights, NY (US);
Michael P. Chudzik, Danbury, CT (US);
Bruce B. Doris, Brewster, NY (US);
Michael A. Gribelyuk, Stamford, CT (US);
Young-Hee Kim, Yorktown Heights, NY (US);
Barry P. Linder, Hastings-on-Hudson, NY (US);
Vijay Narayanan, New York, NY (US);
Joseph S. Newbury, Irvington, NY (US);
Vamsi K. Paruchuri, New York, NY (US);
Michelle L. Steen, Danbury, CT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
The present invention relates to complementary metal-oxide-semiconductor (CMOS) circuits that each contains at least a first and a second gate stacks. The first gate stack is located over a first device region (e.g., an n-FET device region) in a semiconductor substrate and comprises at least, from bottom to top, a gate dielectric layer, a metallic gate conductor, and a silicon-containing gate conductor. The second gate stack is located over a second device region (e.g., a p-FET device region) in the semiconductor substrate and comprises at least, from bottom to top, a gate dielectric layer and a silicon-containing gate conductor. The first and second gate stacks can be formed over the semiconductor substrate in an integrated manner by various methods of the present invention.