The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 19, 2013
Filed:
Nov. 25, 2009
Pamela S. Gillis, Jericho, VT (US);
Jack R. Smith, South Burlington, VT (US);
Tad J. Wilder, South Hero, VT (US);
Francis Woytowich, Charlotte, VT (US);
Tian Xia, Essex Junction, VT (US);
Pamela S. Gillis, Jericho, VT (US);
Jack R. Smith, South Burlington, VT (US);
Tad J. Wilder, South Hero, VT (US);
Francis Woytowich, Charlotte, VT (US);
Tian Xia, Essex Junction, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
The invention disclosed herein provides increased effectiveness of delay and transition fault testing. The method of delay fault testing integrated circuits comprises the steps of creating a plurality of test clock gating groups. The plurality of test clock gating groups comprising elements defining inter-element signal paths within the integrated circuit. Each of the elements of the plurality of test clock gating groups share clock frequency and additional shared characteristics. At least one test signal is commonly and selectively connected through at least one low-speed gate transistor to each of the elements comprising each of the plurality of test clock gating groups based on membership in the test clock gating group. This invention can also be practiced using scan-enable gating groups for the same purposes.