The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 19, 2013

Filed:

Jun. 16, 2011
Applicants:

Zvi Or-bach, San Jose, CA (US);

Deepak C. Sekar, San Jose, CA (US);

Brian Cronquist, San Jose, CA (US);

Israel Beinglass, Sunnyvale, CA (US);

Jan Lodewijk DE Jong, Cupertino, CA (US);

Inventors:

Zvi Or-Bach, San Jose, CA (US);

Deepak C. Sekar, San Jose, CA (US);

Brian Cronquist, San Jose, CA (US);

Israel Beinglass, Sunnyvale, CA (US);

Jan Lodewijk de Jong, Cupertino, CA (US);

Assignee:

MonolithIC 3D Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/58 (2006.01); H01L 23/528 (2006.01); H01L 21/98 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor device comprising: a first single crystal silicon layer comprising first transistors, first alignment mark, and at least one metal layer overlying said first single crystal silicon layer, wherein said at least one metal layer comprises copper or aluminum more than other materials; a second layer overlying said at least one metal layer, said second layer comprising second transistors, second alignment mark, and a through via through said second layer, wherein said through via is a part of a connection path between said first transistors and said second transistors, wherein alignment of said through via is based on said first alignment mark and said second alignment mark and effected by a distance between said first alignment mark and said second alignment mark.


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