The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 19, 2013

Filed:

Jun. 12, 2009
Applicants:

Kevin Sean Matocha, Rexford, NY (US);

Gregory Keith Dudoff, Clifton Park, NY (US);

William Gregg Hawkins, Rexford, NY (US);

Zachary Matthew Stum, Niskayuna, NY (US);

Stephen Daley Arthur, Glenville, NY (US);

Dale Marius Brown, Niskayuna, NY (US);

Inventors:

Kevin Sean Matocha, Rexford, NY (US);

Gregory Keith Dudoff, Clifton Park, NY (US);

William Gregg Hawkins, Rexford, NY (US);

Zachary Matthew Stum, Niskayuna, NY (US);

Stephen Daley Arthur, Glenville, NY (US);

Dale Marius Brown, Niskayuna, NY (US);

Assignee:

General Electric Company, Niskayuna, NY (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/28 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention provides a method of fabricating a metal oxide semiconductor field effect transistor. The method includes the steps of forming a source region on a silicon carbide layer and annealing the source region. A gate oxide layer is formed on the source region and the silicon carbide layer. The method further includes providing a gate electrode on the gate oxide layer and disposing a dielectric layer on the gate electrode and the gate oxide layer. The method further includes etching a portion of the dielectric layer and a portion of the gate oxide layer to form sidewalls on the gate electrode. A metal layer is disposed on the gate electrode, the sidewalls and the source region. The method further includes forming a gate contact and a source contact by subjecting the metal layer to a temperature of at least about 800° C. The gate contact and the source contact comprise a metal silicide. The distance between the gate contact and the source contact is less than about 0.6 μm. A vertical SiC MOSFET is also provided.


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