The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 12, 2013

Filed:

May. 12, 2009
Applicants:

Louis Chao-chiuan Liu, Hsin-Chu, TW;

Lee-chung LU, Taipei, TW;

Yao-ching Ku, Hsinchu, TW;

Inventors:

Louis Chao-Chiuan Liu, Hsin-Chu, TW;

Lee-Chung Lu, Taipei, TW;

Yao-Ching Ku, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of designing an integrated circuit ('IC') is provided that includes placing an IC design, where the IC design includes a first element, a second element, and a path coupling the first and second elements, and routing the IC design. Further, the method includes obtaining at least one of resistivity data and capacitance data related to the path, and obtaining timing data related to the path. The method also includes using at least one of the resistivity data, the capacitance data, and the timing data to determine a critical dimension ('CD') bias to be applied to the path, and modifying the IC design, where modifying includes applying the CD bias to the path.


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