The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 12, 2013

Filed:

Sep. 01, 2010
Applicants:

John A. Harada, Mountain View, CA (US);

Robert J. Drost, Los Altos, CA (US);

David C. Douglas, Palo Alto, CA (US);

Inventors:

John A. Harada, Mountain View, CA (US);

Robert J. Drost, Los Altos, CA (US);

David C. Douglas, Palo Alto, CA (US);

Assignee:

Oracle America, Inc., Redwood Shores, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H01L 21/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

An assembly component and a technique for assembling a chip package using the assembly component are described. This chip package includes a set of semiconductor dies that are arranged in a stack in a vertical direction, which are offset from each other in a horizontal direction to define a stepped terraced at one side of the vertical stack. Moreover, the chip package may be assembled using the assembly component. In particular, the assembly component may include a housing having another stepped terrace. This other stepped terrace may include a sequence of steps in the vertical direction, which are offset from each other in the horizontal direction. Furthermore, the housing may be configured to mate with the set of semiconductor dies such that the set of semiconductor dies are arranged in the stack in the vertical direction. For example, the other stepped terrace may approximately be a mirror image of the stepped terrace.


Find Patent Forward Citations

Quick Actions:

Harada, John. (2013). Manufacturing fixture for a ramp-stack chip package using solder for coupling a ramp component (U.S. Patent No. 8373280). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8373280

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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