The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 12, 2013

Filed:

Sep. 02, 2011
Applicants:

Tzung Han Lee, Taipei, TW;

Chung-lin Huang, Taoyuan County, TW;

Ron Fu Chu, Taipei, TW;

Inventors:

Tzung Han Lee, Taipei, TW;

Chung-Lin Huang, Taoyuan County, TW;

Ron Fu Chu, Taipei, TW;

Assignee:

Inotera Memories, Inc., Taoyuan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/788 (2006.01);
U.S. Cl.
CPC ...
Abstract

A NAND type flash memory for increasing data read/write reliability includes a semiconductor substrate unit, a base unit, and a plurality of data storage units. The semiconductor substrate unit includes a semiconductor substrate. The base unit includes a first dielectric layer formed on the semiconductor substrate. The data storage units are formed on the first dielectric layer. Each data storage unit includes two floating gates formed on the first dielectric layer, two inter-gate dielectric layers respectively formed on the two floating gates, two control gates respectively formed on the two inter-gate dielectric layers, a second dielectric layer formed on the first dielectric layer, between the two floating gates, between the two inter-gate dielectric layers, and between the two control gates, and a third dielectric layer formed on the first dielectric layer and surrounding and connecting with the two floating gates, the two inter-gate dielectric layers, and the two control gates.


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