The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 12, 2013

Filed:

Sep. 29, 2007
Applicants:

Mou-shiung Lin, Hsin-Chu, TW;

Jin-yuan Lee, Hsin-Chu, TW;

Chien-kang Chou, Tainan Hsien, TW;

Inventors:

Mou-Shiung Lin, Hsin-Chu, TW;

Jin-Yuan Lee, Hsin-Chu, TW;

Chien-Kang Chou, Tainan Hsien, TW;

Assignee:

Megica Corporation, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/52 (2006.01); H01L 23/528 (2006.01); H01L 21/70 (2006.01);
U.S. Cl.
CPC ...
Abstract

An integrated circuit chip includes a silicon substrate, a first circuit in or over said silicon substrate, a second circuit device in or over said silicon substrate, a dielectric structure over said silicon substrate, a first interconnecting structure in said dielectric structure, a first pad connected to said first node of said voltage regulator through said first interconnecting structure, a second interconnecting structure in said dielectric structure, a second pad connected to said first node of said internal circuit through said second interconnecting structure, a passivation layer over said dielectric structure, wherein multiple opening in said passivation layer exposes said first and second pads, and a third interconnecting structure over said passivation layer and over said first and second pads.


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