Vertical channel transistors and methods for fabricating vertical channel transistors

Abstract

Provided are a vertical channel transistor and a method for fabricating a vertical channel transistor. The method includes forming an active layer on a substrate, forming a plurality of vertical channels on the active layer, forming a plurality of isolated gate electrodes to surround sidewalls of the plurality of vertical channels, forming a buried bitline to extend along the active layer between the plurality of vertical channels, forming a plug-in between the plurality of vertical channels to connect the plurality of isolated gate electrodes and forming a wordline on a location where the plug-in and the plurality of isolated gate electrodes are connected.