The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8372706 B1

PDF
Full Text
Expired
Date of Patent:
Feb. 12, 2013

Filed:

Aug. 26, 2011
Applicants:

Shun-jang Liao, Pingjhen, TW;

Sheng-chen Chung, Jhubei, TW;

Kong-beng Thei, Hsin-Chu County, TW;

Harry Chuang, Hsin-Chu, TW;

Inventors:

Shun-Jang Liao, Pingjhen, TW;

Sheng-Chen Chung, Jhubei, TW;

Kong-Beng Thei, Hsin-Chu County, TW;

Harry Chuang, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
Abstract

Provided is a method of fabricating a semiconductor device. A first hard mask layer is formed on a substrate. A second hard mask layer s formed the substrate overlying the first hard mask layer. A dummy gate structure on the substrate is formed on the substrate by using at least one of the first and the second hard mask layers to pattern the dummy gate structure. A spacer element is formed adjacent the dummy gate structure. A strained region on the substrate adjacent the spacer element (e.g., abutting the spacer element). The second hard mask layer and the spacer element are then removed after forming the strained region.


Find Patent Forward Citations

Liao, Shun-Jang. (2013). Semiconductor device fabrication method including hard mask and sacrificial spacer elements (U.S. Patent No. 8372706). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8372706

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