The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 05, 2013

Filed:

Jul. 13, 2010
Applicants:

Satish Padmanabhan, Sunnyvale, CA (US);

Plus NG, Hillsboro, OR (US);

Anand Pandurangan, Bangalore, IN;

Suresh Kadiyala, Cupertino, CA (US);

Ananth Durbha, San Jose, CA (US);

Tak Shigihara, Saratoga, CA (US);

Inventors:

Satish Padmanabhan, Sunnyvale, CA (US);

Plus Ng, Hillsboro, OR (US);

Anand Pandurangan, Bangalore, IN;

Suresh Kadiyala, Cupertino, CA (US);

Ananth Durbha, San Jose, CA (US);

Tak Shigihara, Saratoga, CA (US);

Assignee:

Algotochip Corporation, Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/455 (2006.01); G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

Systems and methods are disclosed to automatically design a custom integrated circuit based on algorithmic process or code as input and using highly automated tools that requires virtually no human involvement is disclosed. The method includes receiving a specification of the custom integrated circuit including computer readable code and one or more constraints on the custom integrated circuit; automatically generating a computer architecture for the computer readable code that best fits the constraints; automatically determining an instruction execution sequence based on the code profile and reassigning or delaying the instruction sequence to spread operation over one or more processing blocks to reduce hot spots; continuously evaluating and optimizing one or more factors including physical implementation, and local and global area, timing, or power at an architecture level above RTL or gate-level synthesis; automatically generating a software development kit (SDK) and the associated firmware automatically to execute the computer readable code on the custom integrated circuit; automatically generating associated test suites and vectors for the computer readable code on the custom integrated circuit; and automatically synthesizing the designed architecture and generating a computer readable description of the custom integrated circuit for semiconductor fabrication.


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