The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 05, 2013
Filed:
Jun. 25, 2010
Chuck Alpert, Austin, TX (US);
Zhuo LI, Austin, TX (US);
Michael David Moffitt, Austin, TX (US);
Chin Ngai Sze, Austin, TX (US);
Paul G Villarrubia, Austin, TX (US);
Chuck Alpert, Austin, TX (US);
Zhuo Li, Austin, TX (US);
Michael David Moffitt, Austin, TX (US);
Chin Ngai Sze, Austin, TX (US);
Paul G Villarrubia, Austin, TX (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method, system, and computer usable program product for buffer-aware routing in integrated circuit design are provided in the illustrative embodiments. The design has cells, and the circuit includes buffers and wires. A route is received from a set of routes. The route couples a first point in the circuit to a second point in the circuit and including at least one buffer between the first point and the second point. A determination is made whether the route violates a set of hard constraints for a part of the circuit, where the set of hard constraints includes a reach length constraint. In response to the route not violating any hard constraint in the set of hard constraints, the route is selected as a buffer-aware routing solution between the first and the second points in the circuit.