The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 05, 2013

Filed:

Feb. 11, 2011
Applicant:

Yukio Hayakawa, Fukushima-ken, JP;

Inventor:

Yukio Hayakawa, Fukushima-ken, JP;

Assignee:

Spansion LLC, Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/02 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor device includes an insulation layer () provided on a semiconductor substrate (), a p-type semiconductor region () provided on the insulation layer, an isolation region () provided that surrounds the p-type semiconductor region to reach the insulation layer, an n-type source region () and an n-type drain region () provided on the p-type semiconductor region, a charge storage region () provided above the p-type semiconductor region between the n-type source region and the n-type drain region, and an voltage applying portion that applies a different voltage to the p-type semiconductor region while any of programming, erasing and reading a different data of a memory cell that has the charge storage region is being preformed.


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Hayakawa, Yukio. (2013). Semiconductor device and control method therefor (U.S. Patent No. 8369161). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8369161

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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