The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 05, 2013
Filed:
Mar. 22, 2011
Yong-soon Choi, Yongin-si, KR;
Ha-young Yi, Seongnam-si, KR;
Gil-heyun Choi, Seoul, KR;
Eunkee Hong, Seongnam-si, KR;
Sang-hoon Ahn, Hwaseong-si, KR;
Yong-Soon Choi, Yongin-si, KR;
Ha-Young Yi, Seongnam-si, KR;
Gil-Heyun Choi, Seoul, KR;
Eunkee Hong, Seongnam-si, KR;
Sang-Hoon Ahn, Hwaseong-si, KR;
Samsung Electronics Co., Ltd., Gyeonggi-do, KR;
Abstract
Example embodiments herein relate to a method of fabricating a semiconductor device. The method may include forming a liner insulating layer on a surface of a gate pattern to have a first thickness. Subsequently, a gap fill layer may be formed on the liner insulating layer by flowable chemical vapor deposition (FCVD) or spin-on-glass (SOG). The liner insulating layer and the gap fill layer may be recessed such that the liner insulating layer has a second thickness, which is smaller than the first thickness, in the region in which a metal silicide will be formed. Metal silicide may be formed on the plurality of gate patterns to have a relatively uniform thickness using the difference in thickness of the liner insulating layer.