The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8365115 B1

PDF
Full Text
Expired
Date of Patent:
Jan. 29, 2013

Filed:

Dec. 03, 2009
Applicants:

Louis Chao-chiuan Liu, Hsin-Chu, TW;

Morly Hsieh, Sunnyvale, CA (US);

Dei-pei Liu, Taipei, TW;

Inventors:

Louis Chao-Chiuan Liu, Hsin-Chu, TW;

Morly Hsieh, Sunnyvale, CA (US);

Dei-Pei Liu, Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A system and method for performance modeling of integrated circuits is provided. A method for performing timing analysis on an integrated circuit is provided, the integrated circuit having a timing path. The method includes computing a number of non-common timing path elements in the timing path, assigning a timing de-rate factor to the timing path based on the number of non-common timing path elements, and computing a timing analysis on the integrated circuit using the assigned timing de-rate factor.


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Liu, Louis Chao-Chiuan. (2013). System and method for performance modeling of integrated circuits (U.S. Patent No. 8365115). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8365115

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