The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 29, 2013

Filed:

Jan. 13, 2010
Applicants:

Kenji Takahashi, Tokyo, JP;

Kiyohiro Furutani, Tokyo, JP;

Inventors:

Kenji Takahashi, Tokyo, JP;

Kiyohiro Furutani, Tokyo, JP;

Assignee:

Elpida Memory, Inc., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G05F 1/10 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor device includes two functional circuits, PMOS transistors and NMOS transistors. The PMOS transistors control whether or not a power supply potential is to be delivered to functional circuits, and the NMOS transistors control whether or not a power supply potential GND is to be delivered to the functional circuits. An external terminal supplied with a third power supply potential and another external terminal is supplied with a fourth power supply potential higher than the third power supply potential. A power supply control circuit delivers a control signal, having the fourth power supply potential as amplitude, to transistors to control the electrically conducting state or the electrically non-conducting state of transistors. The power supply control circuit also delivers a control signal, having the third power supply potential as amplitude, to transistors to control the electrically conducting or non-conducting state of the NMOS transistors.


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