The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 29, 2013

Filed:

Nov. 08, 2007
Applicants:

Ahmed Busnaina, Ashland, MA (US);

Mehmet R. Dokmeci, Brookline, MA (US);

Nishant Khanduja, Boston, MA (US);

Selvapraba Selvarasah, Malden, MA (US);

Xugang Xiong, Boston, MA (US);

Prashanth Makaram, Boston, MA (US);

Chia-ling Chen, Boston, MA (US);

Inventors:

Ahmed Busnaina, Ashland, MA (US);

Mehmet R. Dokmeci, Brookline, MA (US);

Nishant Khanduja, Boston, MA (US);

Selvapraba Selvarasah, Malden, MA (US);

Xugang Xiong, Boston, MA (US);

Prashanth Makaram, Boston, MA (US);

Chia-Ling Chen, Boston, MA (US);

Assignee:

Northeastern University, Boston, MA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01);
U.S. Cl.
CPC ...
Abstract

An assembly of nanoelements forms a three-dimensional nanoscale circuit interconnect for use in microelectronic devices. A process for producing the circuit interconnect includes using dielectrophoresis by applying an electrical field across a gap between vertically displaced non-coplanar microelectrodes in the presence of a liquid suspension of nanoelements such as nanoparticles or single-walled carbon nanotubes to form a nanoelement bridge connecting the microelectrodes. The assembly process can be carried out at room temperature, is compatible with conventional semiconductor fabrication, and has a high yield. The current-voltage curves obtained from the nanoelement bridge demonstrate that the assembly is functional with a resistance of −40 ohms for gold nanoparticles. The method is suitable for making high density three-dimensional circuit interconnects, vertically integrated nanosensors, and for in-line testing of manufactured conductive nanoelements.


Find Patent Forward Citations

Loading…