The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 29, 2013
Filed:
Aug. 09, 2010
Yoshitaka Sasaki, Milpitas, CA (US);
Hiroyuki Ito, Milpitas, CA (US);
Hiroshi Ikejima, Hong Kong, CN;
Atsushi Iijima, Hong Kong, CN;
Yoshitaka Sasaki, Milpitas, CA (US);
Hiroyuki Ito, Milpitas, CA (US);
Hiroshi Ikejima, Hong Kong, CN;
Atsushi Iijima, Hong Kong, CN;
Headway Technologies, Inc., Milpitas, CA (US);
SAE Magnetics (H.K.) Ltd., Hong Kong, CN;
Abstract
A layered chip package includes a main body, and wiring that includes a plurality of wires disposed on a side surface of the main body. The main body includes: a main part including a plurality of layer portions; a plurality of first terminals disposed on the top surface of the main part and connected to the wiring; and a plurality of second terminals disposed on the bottom surface of the main part and connected to the wiring. Each layer portion includes a semiconductor chip. The plurality of second terminals are positioned to overlap the plurality of first terminals as viewed in a direction perpendicular to the top surface of the main body. A plurality of pairs of first and second terminals that are electrically connected via the wires include a plurality of pairs of a first terminal and a second terminal that are positioned not to overlap each other.