The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 29, 2013
Filed:
Jan. 28, 2011
Zvi Or-bach, San Jose, CA (US);
Brian Cronquist, San Jose, CA (US);
Israel Beinglass, Sunnyvale, CA (US);
Jan Lodewijk DE Jong, Cupertino, CA (US);
Deepak C. Sekar, San Jose, CA (US);
Paul Lim, Fremont, CA (US);
Zvi Or-Bach, San Jose, CA (US);
Brian Cronquist, San Jose, CA (US);
Israel Beinglass, Sunnyvale, CA (US);
Jan Lodewijk de Jong, Cupertino, CA (US);
Deepak C. Sekar, San Jose, CA (US);
Paul Lim, Fremont, CA (US);
MonolithIC 3D Inc., San Jose, CA (US);
Abstract
A semiconductor device including a first layer including first transistors, wherein first logic circuits are constructed by the first transistors, and wherein the first logic circuits include at least one of Inverter, NAND gate, or NOR gate; and a second layer overlaying said first layer, the second layer including second transistors, wherein second logic circuits are constructed by the second transistors; wherein each logic circuit in the first logic circuits has inputs and at least one first output, the inputs are connected to the second logic circuits; wherein each logic circuit in the second logic circuits has a second output, and wherein the first transistors include first selectors adapted to selectively replace at least one of the at least one first outputs with at least one of the second outputs.