The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 22, 2013
Filed:
Oct. 14, 2011
Chung-hsing Wang, Baoshan Township, Hsinchu County, TW;
Chih Sheng Tsai, Houli Shiang, TW;
Ying-lin Liu, Hsinchu, TW;
Kai-yun Lin, Hsinchu, TW;
Chung-Hsing Wang, Baoshan Township, Hsinchu County, TW;
Chih Sheng Tsai, Houli Shiang, TW;
Ying-Lin Liu, Hsinchu, TW;
Kai-Yun Lin, Hsinchu, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
A method of designing and verifying 3D integrated circuits (3D IC) including providing a first layout corresponding to a first device of a 3D IC. The first layout includes a first interface layer. A second layout corresponding to a second device of the 3D IC is also provided. The second layout includes a second interface layer. A verification of the 3D is performed by verifying the first and second interface layers. The verification includes performing at least one of a design rule check (DRC) or a layout-versus-schematic (LVS) on the first and/or second interface layers.