The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 22, 2013

Filed:

Jan. 14, 2011
Applicants:

Chong-kwang Chang, Incheon, KR;

Sung-hon Chi, Seoul, KR;

Hong-jae Shin, Seoul, KR;

Yong-jin Chung, Suwon-si, KR;

Young-mook OH, Hwaseong-si, KR;

Ju-beom Yi, Suwon-si, KR;

Inventors:

Chong-Kwang Chang, Incheon, KR;

Sung-Hon Chi, Seoul, KR;

Hong-Jae Shin, Seoul, KR;

Yong-Jin Chung, Suwon-si, KR;

Young-Mook Oh, Hwaseong-si, KR;

Ju-Beom Yi, Suwon-si, KR;

Assignee:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of manufacturing a semiconductor device, the method including providing a semiconductor substrate; forming a gate pattern on the semiconductor substrate such that the gate pattern includes a gate dielectric layer and a sacrificial gate electrode; forming an etch stop layer and a dielectric layer on the semiconductor substrate and the gate pattern; removing portions of the dielectric layer to expose the etch stop layer; performing an etch-back process on the etch stop layer to expose the sacrificial gate electrode; removing the sacrificial gate electrode to form a trench; forming a metal layer on the semiconductor substrate including the trench; removing portions of the metal layer to expose the dielectric layer; and performing an etch-back process on the metal layer to a predetermined target.


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