The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 15, 2013
Filed:
Oct. 19, 2010
Tom Burd, Fremont, CA (US);
Yuri Apanovich, San Jose, CA (US);
Srinivasaraghavan Krishnamoorthy, Mountain View, CA (US);
Vishak Kumar Venkatraman, Santa Clara, CA (US);
Anand Daga, Cupertino, CA (US);
Tom Burd, Fremont, CA (US);
Yuri Apanovich, San Jose, CA (US);
Srinivasaraghavan Krishnamoorthy, Mountain View, CA (US);
Vishak Kumar Venkatraman, Santa Clara, CA (US);
Anand Daga, Cupertino, CA (US);
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
A system and method for providing a statistical budgeting approach to modeling reliability effects such as interconnect electromigration (EM), transistor time-dependant dielectric breakdown (TDDB), hot-carrier injection effects (HCI) and bias temperature instability (BTI) is disclosed. A static analysis flow captures the effects of design topology, switching constraints, interactions between signal nets and supply rails as well as thermal gradients due to interconnect and transistor self as well as mutual heating, and was used to verify successive iterations of deep sub-micron integrated circuit designs.