The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 15, 2013

Filed:

Oct. 22, 2010
Applicants:

Shawn Searles, Austin, TX (US);

Nicholas T. Humphries, Austin, TX (US);

Brian W. Amick, Bedford, MA (US);

Richard W. Reeves, Westborough, MA (US);

Hanwoo Cho, Acton, MA (US);

Ronald L. Pettyjohn, Concord, MA (US);

Inventors:

Shawn Searles, Austin, TX (US);

Nicholas T. Humphries, Austin, TX (US);

Brian W. Amick, Bedford, MA (US);

Richard W. Reeves, Westborough, MA (US);

Hanwoo Cho, Acton, MA (US);

Ronald L. Pettyjohn, Concord, MA (US);

Assignee:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A physical memory interface (Phy) and method of operating is disclosed. The Phy interface includes command and status registers (CSRs) configured to receive a first power context and second power context. Selection circuitry is configured to switch between the first and second power contexts. A plurality of adjustable delay elements are provided, each having a delay time responsive to the selected power context. A first set of CSRs configured may store the first power context and a second set of CSRs configured may store the second power context. The Phy interface may also include a plurality of drivers each having a selectable drive strength responsive to the selected power context. The Phy interface may also include a plurality of receivers each having a selectable termination impedance responsive to the selected power context. Switching between power contexts may result in adjusting of the delay elements, drive strength and/or termination impedance of one or more drivers/receivers.


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