The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 15, 2013
Filed:
Oct. 22, 2010
Applicants:
Yuji Nakaoka, Tokyo, JP;
Hiroshi Ichikawa, Tokyo, JP;
Inventors:
Yuji Nakaoka, Tokyo, JP;
Hiroshi Ichikawa, Tokyo, JP;
Assignee:
Elpida Memory, Inc., Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/06 (2006.01);
U.S. Cl.
CPC ...
Abstract
When an I/O number is 8 bit, a semiconductor device includes a first memory mat that is selected when Xis (0) and Xand Xare (0, 0), a second memory mat that is selected when Xis (1) and Xand Xare (0, 0), and a third memory mat that is selected irrespective of a value of Xwhen Xand Xare (0, 0). When the I/O number is 16 bit, Xis ignored, and the first to third memory mats are selected when Xand Xare (0, 0). In this manner, because the third memory mat is shared between so-called upper side and lower side, control is prevented from becoming complicated and an area is prevented from increasing.