The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 15, 2013
Filed:
May. 17, 2010
Hsung Jai Im, San Jose, CA (US);
Henley Liu, San Jose, CA (US);
Jae-gyung Ahn, Pleasanton, CA (US);
Tony Le, San Jose, CA (US);
Patrick J. Crotty, San Jose, CA (US);
Hsung Jai Im, San Jose, CA (US);
Henley Liu, San Jose, CA (US);
Jae-Gyung Ahn, Pleasanton, CA (US);
Tony Le, San Jose, CA (US);
Patrick J. Crotty, San Jose, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
A technique for setting Vgg in an IC is disclosed. The technique includes specifying a design reliability lifetime for the IC, and a relationship between maximum gate bias and gate dielectric thickness for the IC sufficient to achieve the design reliability lifetime is established. The IC is fabricated and the gate dielectric thickness is measured. A maximum gate bias voltage is determined according to the gate dielectric thickness and the relationship between maximum gate bias and gate dielectric thickness, and a Vgg trim circuit of the IC is set to provide Vgg having the maximum gate bias voltage that will achieve the design reliability lifetime according to the measured gate dielectric thickness.