The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 15, 2013
Filed:
Dec. 22, 2010
Applicants:
Chen-chin Liu, Hsinchu, TW;
Lan Ting Huang, Kaohsiung, TW;
Ling Kuey Yang, Changhua, TW;
Po Hsuan Wu, Hsinchu, TW;
Inventors:
Chen-Chin Liu, Hsinchu, TW;
Lan Ting Huang, Kaohsiung, TW;
Ling Kuey Yang, Changhua, TW;
Po Hsuan Wu, Hsinchu, TW;
Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/3205 (2006.01); H01L 21/4763 (2006.01);
U.S. Cl.
CPC ...
Abstract
A method for fabricating a floating gate memory device comprises using a buried diffusion oxide that is below the floating gate thereby producing an increased step height between the floating gate and the buried diffusion oxide. The increased step height can produce a higher GCR, while still allowing decreased cell size using a virtual ground array design.
Liu, Chen-Chin. (2013). Apparatus and associated method for making a floating gate cell with increased overlay between the control gate and floating gate (U.S. Patent No. 8354335). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8354335
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile